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Editorial

Peggy Aycinena
EDA Weekly
The Best of Times, The Worst of Time: Part 2 Since Part 1 of this article was published on October 13th, events have begun to overwhelm. The dramatic speed with which the …

Mark Gilbert
Careers Corner
Remember that kids' nursery rhyme LAYOFFS, FREEZES, GENERAL DOWNTURN… O MY?

Dr. Russ Henke & Dr. Jack Horgan
EDA & IP Commentary
Commentary: Electronics IP Industry - A November 2008 Update

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Jobs

Architectural Peformance Software Architect for Sun Microsystems at Santa Clara, CA

Design For Manufacturing Engineer / Physical Design Verification for Sun Microsystems at santa Clara, CA

Software Technical Lead for Sun Microsystems at Santa Clara, CA

Circuit Design Engineer for Sun Microsystems at Santa Clara, CA

Chip Integration Lead for Sun Microsystems at Santa Clara, CA

Sr. STATIC TIMING and/or POWER ENGINEERS R&D for EDA Careers at San Jose, CA

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Books For Sale

Microelectronic Circuit Design with CD-ROM, by Richard C. Jaeger, Travis N. Blalock.

LogixPro Simulation Lab/Exercises Manual w/ Student CD, by Frank Petruzella.

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Upcoming Events

DASIP 2008 at Université Libre de Bruxelles Belgium - Nov 24 - 26, 2008

SPS/IPC/DRIVES 2008 at Karl-Schönleben-Strasse Nuremberg Germany - Nov 25 - 27, 2008

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Tutorials

MT-005: Noise Power Ratio (NPR) – A 65-Year Old Telephone System Specification Finds New Life in Modern Wireless Applications

Verilogger Pro Animated Tutorial

ADC Architectures III: Sigma-Delta ADC Basics

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